Smart chip could slash computing energy use by up to 5,000×
Researchers in Italy have recently developed a new smart chip that could greatly reduce energy consumption while accelerating computation in high-performance computing systems and data centers.
Created by a research team led by Daniele lelmini, PhD, a professor at Politecnico di Milano’s Department of Electronics, Information and Bioengineering, the novel device showcases a different approach to computer architecture.
It highlights how analogue in-memory computing can overcome one of the most crucial limitations of modern computers, by reducing the need to continuously move data between the memory and the processor.
Ielmini, who is also the study’s corresponding author, noted:
The integrated chip demonstrates the feasibility on an industrial scale of a revolutionary concept such as analogue computation in memory,
New chip is a fully integrated analogue accelerator
The scientists’ work is part of the ERC-funded ANIMATE (ANalogue In-Memory computing with Advanced device TEchnology) project. The initiative received the Advanced Grant in 2022, which offers up to USD 2.9 million (EUR 2.5 million) over a period of five years.
As per the team, traditional digital computers consume large amounts of energy because of computation and because data must be repeatedly moved between memory and processing units.
In the meantime, in-memory computing addresses this inefficiency by performing calculations directly within the memory array, thus significantly reducing internal data traffic.
The ANIMATE project aimed to design the device technology, circuit and system architectures, along with applications to validate CL-IMC. It was carried out through an international collaboration, including scientists from Peking University.
The project is based on Ielmini’s preliminary work into closed-loop in-memory computing (CL-IMC), highlighting its potential for faster computation while using up to 5,000 times less energy than digital systems.
The new chip is a fully integrated analogue accelerator that can solve both linear and non-linear systems of equations. Made with standard CMOS (Complementary Metal-Oxide-Semiconductor) technology, it is compatible with existing silicon manufacturing processes.
The future of computing
The device utilizes two 64-by-64 arrays of programmable resistive memory cells. These arrays function like ordered grids. Each intersection represents a memory element.
The cells are based on SRAM (Static Random-Access Memory), a type of fast and stable memory. For the chip, the scientists combined it with integrated resistors for programming different levels of resistance.
At the same time, the chip’s architecture is enhanced by on-chip analogue parts, among which operational amplifiers and analogue-to-digital converters. Since it performs computation inside the memory itself, the chip can handle complex calculations without relying on an external processor.
In tests, the chip matched the accuracy of conventional digital systems. However, it consumed less power. It also delivered lower computing latency and required a smaller footprint on the silicon.
Ielmini concluded in a press release,
We are already working on putting this innovation into use in real-world applications to reduce the energy costs of computation, especially in the field of artificial intelligence
The technology is well suited for high-performance, energy-efficient tasks such as AI, big data processing and advanced wireless systems. Potential uses include robotics, navigation systems, data centers and future 5G and 6G networks.
The study has been published in the journal Nature Electronics.
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Smart chip could slash computing energy use by up to 5,000×, source
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