NEO Semiconductor Introduces World’s First Extreme High Bandwidth Memory (X-HBM) Architecture for AI Chips
New X-HBM architecture delivers a 32K-bit wide data bus and potentially 512 Gbit per die density, offering 16X more bandwidth or 10X higher density than traditional HBM
SAN JOSE, Calif., Aug. 5, 2025 /PRNewswire/ — NEO Semiconductor, a leading developer of breakthrough memory technologies, today introduced the world’s first Extreme High Bandwidth Memory (X-HBM) architecture for AI chips. Built to meet the growing demands of generative AI and high-performance computing, X-HBM delivers unmatched performance with a 32K-bit data bus and potentially 512 Gbit per die, dramatically surpassing the limitations of traditional HBM with 16X greater bandwidth or 10X higher density.
Andy Hsu, Founder & CEO of NEO Semiconductor, said:
X-HBM is not an incremental upgrade, it’s a fundamental breakthrough,
“With 16X the bandwidth or 10X the density of current memory technologies, X-HBM gives AI chipmakers a clear path to deliver next-generation performance years ahead of the existing roadmap. It’s a game-changer for accelerating AI infrastructure, reducing energy consumption, and scaling AI capabilities across industries.”
Built on NEO’s proprietary 3D X-DRAM architecture, X-HBM represents a major leap in memory technology by eliminating long-standing limitations in bandwidth and density. In contrast, HBM5, still in development and expected to reach the market around 2030, is projected to support only 4K-bit data buses and 40 Gbit per die. A recent study from the Korea Advanced Institute of Science and Technology (KAIST) projects that even HBM8, expected around 2040, will offer just 16K-bit buses and 80 Gbit per die. In comparison, X-HBM delivers 32K-bit buses and 512 Gbit per die, allowing AI chip designers to bypass a full decade of incremental performance bottlenecks associated with traditional HBM technology.
Key Features and Benefits:
- Scalable – Enables faster data transfer between GPUs and memory for more efficient AI scaling.
- High-Performance – Unlocks untapped GPU capabilities to boost AI workloads.
- Sustainable – Reduces power and hardware needs by consolidating AI infrastructure.
NEO Semiconductor’s CEO, Andy Hsu, will deliver a keynote presentation on August 6, at 11 a.m. PST at FMS: the Future of Memory and Storage, where he will discuss the breakthrough X-HBM technology. The event takes place August 5-7, 2025, at the Santa Clara Convention Center in California, USA. NEO Semiconductor will also be exhibiting at booth #507. To schedule a meeting at FMS 2025, please contact: mayalustig@neosemic.com.
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NEO Semiconductor Introduces World’s First Extreme High Bandwidth Memory (X-HBM) Architecture for AI Chips, source
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